1. Field of the Invention
The present invention relates in general to liquid crystal display devices based on active matrix base, and relates in particular to a structural configuration of the terminal electrodes in the active matrix base.
2. Description of the Related Art
In recent years, liquid crystal display devices have become widely popular because they are thin and light weight, and particular interests are focused on those liquid crystal display devices based on active matrix bases in which each pixel is driven by its own signal switching element. Their attraction is due to their excellent tonal capability and superior response speed, making these display devices attractive for dynamic imaging applications. Switching elements are usually driven by thin film transistor (TFT) or multiple instruction matrix (MIM) elements.
FIG. 22 is a schematic diagram of a TFT-driven active matrix liquid crystal (LC) display device. On a transparent base 100, a plurality of scanning lines 101 and signals lines 102 intersect each other, and a TFT element 105 is fabricated at each intersection. A TFT element is a three-terminal device comprised of three electrodes for each of a semiconductor layer for performing switching operations, a gate terminal and a source/drain terminal. Each TFT element 105 is connected to one pixel electrode 106, and such pairs are distributed in a matrix pattern on the base 100. For the purpose of connecting the base 100 to external drive circuits, the start terminal (one side) of the scanning line 101 is connected to a scanning line terminal 103; while the start terminal (one side) of the signal line 102 is connected to a signal line terminal 104. The external drive circuits are press bonded to the base plate 100 by placing an anisotropic conductive film (ACF) in the middle, between the terminal surfaces and a tape carrier package (TCP), and pressing together the entire base assembly.
The operation of the active matrix display will be explained briefly. When a voltage pulse is applied to a selected terminal Xi, for example, of the scanning lines 101, the gate voltage becomes higher than the threshold voltage, and all the gates in all the TFT 105 connected to this terminal are simultaneously turned on, and signal voltages of the image data are transmitted by each signal line 104 through the one set of source/drain terminals of the live-TFT 105 to the other set of source/drain terminals of the TFT 105 of the opposing base. The other set of source/drain terminals are connected to the pixel electrodes 106 so that the voltage signals are applied to the pixel electrodes 106, thereby generating a voltage difference between the pixel electrodes 106 (with an intervening LC layer 107) and the opposing electrode 108 formed on the opposing base. The LC layer 107 surrounded by the two bases alters its transparency due to the difference in the voltage impressed on two bases, thereby producing an image corresponding to the signal voltage. When the terminal Xi is in a non-selected state, and when the gate voltage drops below the threshold voltage, all the gates connected to these TFT 105 are turned off, and when a next terminal Xi+1 is selected, all the gates of the TFT 105 connected to this line are turned on, and the above process is repeated. The image does not disappear instantly when the gate voltages are turned off, because the voltage difference applied to the LC layer 107, between the pixel electrodes 106 and the opposing electrodes 108, is maintained primarily due to the static capacitance of the two electrodes until the same scanning line is selected again, and new image signal voltages are applied.
In active matrix bases using amorphous silicon (a-silicon) for the semiconductor layer to fabricate TFT or MIM elements, connecting electrodes to the external drive circuits are made on the scanning line terminals 103 and signal line terminals 104 in the start terminals of each scanning line, and they are operated as discussed above in the case of the TFT technology. Typical requirements for connecting electrodes are that: the contact electrical resistance is low and stable, the joint has high reliability for water resistance and the base can withstand repeat of press bonding operations.
For example, a Japanese Patent Application, First Publication, H1-205460 (referred to as Reference 1) discloses a general type of terminal construction, and a method of making peel-resistant terminals on thin film arrayed transistor base. FIG. 23 in Reference 1 shows a cross sectional view of a first example of an electrical conductive layer of a terminal section comprising a metal film and a transparent conductive overlay. The scanning line terminal 103a of the scanning line 101a on a transparent base 1 is configured in such a way that a metal film 202 (made at the same time as the signal lines) contact the start terminals of the scanning lines 101a through a contact hole 12 fabricated on the gate insulation film 201, and a transparent conductive film 203 is overlaid on the metal film 202. A variation of the structure is disclosed is a channel protection type TFT including an n-type a-silicon layer beneath the metal film 202.
FIG. 24 shows a cross sectional view of a second example in which a terminal configuration comprises a single layer of transparent conductive film 203 in the electrical conduction layer. The second example does not have the metal film 202 used in the first example, and the scanning line terminal 103b is formed on a single layer of the transparent conductive layer 203 connected to the start terminal of the scanning line 101a.
FIG. 25 is a cross sectional view of a third example of the scanning line terminal configuration comprising a single layer of metal film. In this example, contrary to the first example, there is no transparent conductive film 203, so that the scanning line terminal 103c is comprised by a metal film 202 alone overlaying the start terminal of the scanning line 101a.
The advantages of the method for making such TFT array bases for the channel protection type TFT are as follows. These structures can be produced by first depositing the gate insulation film 201 on the entire surface of the base, then a-silicon layer 204 is deposited selectively, using a metal masking, so as to avoid depositing on the start terminals of the scanning line 101a; in patterning the protective insulation film 205, contact holes 12 can be formed by opening the gate insulation film 201 simultaneously in those regions where the scanning lines 101a are not overlaid with a-silicon film 204; and the conductive layer to serve the function of the contact terminal of the scanning line 101a can be formed simultaneously with source/drain electrodes or signal lines. By following such steps, it is possible to protect, without increasing fabrication steps, the surface of the transparent plate 1 in the vicinity of the terminals of the scanning lines 101 on the transparent base 1 from corrosion during wet etching by such etchant as buffered hydrofluoric acid solution, thereby preventing peeling of the terminals.
However, in this approach, because of the use of metal masking, there are problems of damaging the base and generation of debris particles, as well as non-uniform distribution of film thickness. Furthermore, to improve the transistor performance by maintaining a clean interface between the gate insulation film 201 and a-silicon film 204, it is necessary to carry out both deposition steps serially in the same vacuum atmosphere. However, it is generally not possible to use a metal masking only during the latter deposition step, and even if it can be so arranged, it would necessitate a large scale revisions of the deposition apparatus. Also, the metal film may be made of titanium, but when using metals such as molybdenum and tungsten which are corroded by moisture, there is a serious problem that, even if the metal film 202 is protected with the transparent conductive film 203 (refer to FIG. 23), it is generally not possible to assure reliability of the terminal contact. This problem is the same for the terminal structure shown in FIG. 24 when molybdenum or tungsten is used for the scanning line 101a. This problem is made even more serious in the case of single layer structure of the metal film 202 shown in FIG. 25. Additional problem of the structure in FIG. 25 is that the surface of the metal film 202 is oxidized in the subsequent heat treatment processes (annealing in array fabrication and orientation film sintering in cell fabrication), leading to high initial electrical contact resistance and inferior contact reliability.
Another type of contact structure has been disclosed in a Japanese Patent Application, First Publication, H2-156226 (referred to as Reference 2). In this case, as shown in FIGS. 26A, 26B, both the scanning line terminal 103b and signal line terminal 104b are made of a single layer of transparent conductive film 203-1, 203-2, respectively. This technique is based on the use of low resistance conductive materials (aluminum or molybdenum) for the scanning line 101b and signal line 102b, and is excellent from the standpoint of preventing corrosion and oxidation of the terminal sections. However, there is a problem of the ability of the bonded interface to withstand repeated press bonding.
Technique for preventing oxidation of the metal lines is disclosed, for example, in a Japanese Patent Application, First Publication, H4-364723 (referred to as reference 3). A cross sectional view of an electrode structure of this semiconductor device is shown in FIG. 27. The wiring structure comprises a metal film 244, having a high melting point, is surrounded with nitride films 245, 246 of the metal. This structure is fabricated by: making contact hole 243 on the INSULATION film 242 produced on a semiconductor base 241; depositing, successively, a high melting point metal-nitride film 245 and a high melting point metal film 244 by reactive sputtering; producing wiring patterns by etching back the high melting point metal film 244; and forming a high melting point metal-nitride film 246 over the high melting point metal film 244. The high melting point metal nitride serves as a barrier film, and prevents interlayer reaction between silicon and metal layers at the contact interface, and also enables to prevent oxidation of the wiring during high temperature heat treatment processes. The use of nitride films of high melting point metals, such as silicon nitride, for preventing interlayer reaction between silicon in diffusion layer and metal electrode, is widely utilized in semiconductor device fabrication, and is disclosed, for example, in a Japanese Patent Application, First Publication H2-249264.
In reviewing the problems inherent in the existing technologies, it has been considered that the greatest concerns are: in manufacturing active matrix bases, heat treatment steps introduce oxidation of the conductive surface of the contact electrodes leading to high and unstable contact electrical resistance at the terminals, and that even in cases without such problems, there is a degradation in contact reliability. These problems will be discussed in more detail in the following.
In the third example from the first reference presented in FIG. 25, the first concern is oxidation in the metal film 202 caused by the heat treatment steps (annealing in array fabrication and orientation film sintering in cell fabrication), because it leads to high and unstable initial values of electrical contact resistance (press bonded resistance) to TCP. Also, even if the initial contact resistant is low, storage at high temperature and humidity conditions will lead to high electrical contact resistance. The reason is that, although heat treatment is normally carried out in a nitrogen atmosphere, cooling from heat treatment temperature is carried out sometimes while the substrate temperature is high, and when such a base is exposed to air, a low-conductivity oxide film, which behaves like a semiconductor, is formed on the surface of the metal film 202. The second concern is that when the metal film 202 is made of a low corrosion resistant metals, such as molybdenum and tungsten or their alloys, the contact reliability of the terminals cannot be assured. The reason is that even if the metal parts are protected with an ACF during press bonding and the bonded TCP is covered with a polymer resin, it is not possible to completely protect the metal from infiltration of external moisture.
In the first and second examples shown in FIGS. 23 and 24, the first concern is that, if the thickness of the transparent conductive film 203 is of the order of 100 nm, and when the metal film 202 and scanning lines 101a are made of such corrosion-susceptible metals as molybdenum and tungsten, the reliability of the terminal contact cannot be assured. The reason is that because the transparent conductive film 203 is porous, infiltration of external moisture cannot be prevented. The discussion relating to these examples are based on the assumption of reverse-stagger type (channel protection type) TFT, so the transparent conductive film 203 can be made after the fabrication of scanning lines 101a and signal lines, resulting that the structures shown in FIGS. 23, 24 can be made, without increasing the fabrication steps, and there is no problem of surface oxidation. However, when relating to sequential-stagger type TFT, fabrication of transparent conductive film used for source/drain electrodes is normally required to be carried out before fabricating the scanning line (uppermost layer wiring), and therefore, it is necessary to increase the fabrication steps to produce the structures shown in FIGS. 23 and 24. In other words, the second concern is that to make a terminal structure such as those shown in FIGS. 23 and 24 for a sequential-stagger type TFT, fabrication process normally requires more steps. Such production conditions can easily lead to a poor yield, because the sequential-stagger type TFT uses transparent conductive film at least on some regions of the device, leading to a danger of debris particle generation during the transparent film deposition process.
The first concern regarding the technology presented in Reference 1 (JPA, H1-205460) is, during the use of metal masking, the base may become scratched and particles may be generated, because it is necessary for the mask to be laid in contact with the base to prevent deposits to form around to the back of the masking. The second concern is that non-uniform distribution of film thickness can occur during fabrication with a mask, because a mask must have a certain thickness, and deposit formation near the edges of the mask is affected by a shadowing effect of the mask. As the deposition process is continued, deposit can also accumulate on the mask, the shadowed portion also increases gradually. The third concern is that it is difficult to maintain cleanliness in the interface between the gate INSULATION film 201 and the a-silicon film 204 while they are being deposited serially in the same vacuum environment. The result is a degradation in the properties of the fabricated transistors, because it is normally impossible to use metal masking only during the deposition of the latter film, and even if it was possible, it requires a substantial revision of the deposition apparatus.
In the technology presented in Reference 2 (JPA H2-156226), main concern is that it is difficult to repeat press bonding operations, because when the TCP is peeled off for repeating a press bonding step, the transparent conductive films 203-1 and 203-2 are prone to peeling or otherwise damaged, leading to poor yield and poor reliability.
In the technology presented in Reference 3 (JPA, H4-364723), the first concern is that the metal wiring film is susceptible to peeling, because, particularly in the case of high melting point metal, tungsten film, bonding between the nitride film 245 of the high melting point metal and its substrate material is often inadequate. The second concern is that the fabrication process is complex, because the high temperature melting point metal film 244 must be surrounded on both sides with nitride films 245, 246 of the same high temperature melting point metal. Bonding of nitride film 246 of this high temperature melting point metal requires a special technique, called high pressure nitriding.